Packaging lead inductance is a major design issue, particularly for RF analog chips such as WLAN power amplifiers (PA). For example, the emitter ground leads used in SiGe heterojunction bipolar transistor (HBT) RF designs are normally contacted to the package either using multiple wire bonds or flip chip solder bumps. Wire bond package ground leads have high inductance, on the order of 160 pH, which results in unacceptable PA insertion loss. Although flip chip solder bumps have low inductance, they increase packaging complexity and are expensive.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.